Dynamic Voltage Scaling refers to the scaling of the magnitude of supply voltage to provide a means of power/speed trade-off. Specifically, for higher speed demands, supply voltage is ‘dialled-up’ and conversely ‘dialled-down’ when the demand for speed is modest. FIG. 1 depicts the power dissipation (see bold solid line 101) and speed (see bold dotted line 102) characteristics of a digital circuit for a full range of Dynamic Voltage Scaling, where the supply voltage VDD 103 is adjusted from the nominal voltage regime 104 to the near-threshold voltage regime 105 to the sub-threshold voltage regime 106. In FIG. 1, the readings of the power dissipation 101 and the speed 102 of the digital circuit are normalized to those at the nominal voltage 107. At the sub-threshold voltage regime 106, VDD 103 is even below the threshold voltage 108 of transistors, and the digital circuit still works, although significantly slower by merely using a weak-inversion current for charging and discharging, until at the minimum voltage 109 where the transistors therein fail to switch. Interestingly, in some applications, the maximum energy efficiency point/lowest power dissipation point of a digital circuit can be shown at the sub-threshold voltage regime 106 in a book entitled ‘Sub-threshold Designs for Ultra Low-power Systems’, Springer, 2006, authored by A. Wang, B. H. Calhoun, and A. P. Chandrakasan (herein Wang et al). Thus, operating digital circuits at the sub-threshold voltage regime 106 is highly attractive for ultra-low power dissipation, and when necessary, is suitable for full Dynamic Voltage Scaling for power/speed trade-off.
Sub-threshold operation offers the potential of ultra-low power, including operation at or near the maximum efficiency point or region, albeit very low speed. An important consideration for the practical realization of sub-threshold circuits may be operational robustness, that is their tolerance to process, voltage, and temperature (PVT) variations, whereby the process variations include threshold voltage variations. This difficulty of practical realization may be compounded when smaller geometry nano-scaled fabrication processes are used as these variations become increasingly variable. For example, the process parameter and threshold voltage variations (at nominal VDD) detailed in the International Technology Roadmap for Semiconductors (ITRS-2009) stipulate that these variations will increase from 11% and 42% for the current 45 nm process to 32% and 112% for the impending 9 nm process expected in 2024. These variations may strongly influence the circuit performance. As the effects of PVT variations (and permutations thereof) may be severe and largely unpredictable (or intractable), they may lead to unpredictable sub-threshold circuit performance. This appears to be a seemingly insurmountable obstacle to their acceptance within the electronics community and/or to their practical application, save relatively simple applications, for example wrist watches.
Attempts to accommodate the PVT variations in practical realization of complex digital sub-threshold systems include enforcing strict operating environments (e.g. expensive highly controlled fabrication processes and electrical conditions), transistor upsizing (to reduce the effects of random dopent fluctuations), analog-like current-mode approaches, adaptive body biasing, double-gate MOSFET, self-calibration techniques, redundancy circuitry, and adopting ‘pessimistic’ designs in the sense that large delay safety margins are allowed, etc; the large delay safety margins allowed for would typically include the worst-case delay, including clock skew, setup-time, hold-time for registers, etc. Consequently, designing a system with operation robustness, based on the contemporary and prevalent synchronous-logic design philosophy at the lower range of sub-threshold voltage operation is challenging, largely unsuccessful and/or its operation unnecessarily slower than warranted. This is because in synchronous-logic, a global clock or variants thereof is used for synchronization and every operation must be completed within a clock period. In fact, because a complete profile of the PVT variations is virtually intractable in the sub-threshold voltage regime 106, the circuit operation cannot be guaranteed to be robust (substantially error-free) if the contemporary synchronous-logic design philosophy is adopted. A good description of synchronous-logic design philosophy can be found in a book authored by J. Rabaey, A. Chandrakasan, and B. Nikolic and entitled ‘Digital Integrated Circuits, A Design Perspective’, 2nd Ed. Upper Saddle River, N.J.: Prentice Hall, 2001. The associated design difficulties of synchronous-logic designs for sub-threshold operation can be found in the book by Wang et al.
An alternative digital logic design philosophy for sub-threshold voltage operation is to adopt the somewhat esoteric asynchronous-logic design philosophy, which is clockless or self-timed. There are four general async approaches: Delay-Insensitive, Self-Timed (including bundled-data), Speed-Independent and Quasi-Delay-Insensitive (QDI). Of these, only the QDI async approach offers the most practical approach for sub-threshold operation, significant advantages of design simplicity (in terms of accommodating PVT variations) and operation robustness. It innately detects the computation delays according to different workloads and operating conditions. A good description of asynchronous-logic design philosophy can be found in a book authored by J. Sparso and S. Fuber and entitled Principle of Asynchronous Circuit Design: A Systems Perspective, Norwell M A: Kluwer Academic, 2001 (herein Sparso et al). Further, a good description of the specific QDI approach can be found in a paper authored by A. Martin and M. Nsytrom and entitled ‘Asynchronous Techniques for System-on-chip Designs’, IEEE Proceedings, 2006, and in a book authored by S. C. Smith and J. Di and entitled ‘Designing Asynchronous Circuits using NULL Convention Logic (NCL)’, Morgan & Claypool, 2009 (herein Smith et al).
QDI circuits are typically implemented in either one of three logic families: Dynamic-Logic, Pass-Logic or Static-Logic. Static-Logic circuits may comprise complementary networks of n- and p-transistors. Typically the n-network ties the output to the ground and the p-network ties the output to the supply voltage. The configuration is such that the two networks are mutually exclusive for operation, and the output is connected at every point in time to either the ground or the supply voltage via a low resistance path. The logic output is thus statically stable and no additional circuitry is therefore needed to hold the output at its intended value. This can be contrasted with Dynamic-Logic, which requires temporary storage of signal values which generally rely on the capacitance of high impedance nodes. As a result of this operation, Dynamic-Logic suffers from current leakage and charge sharing, and thus requires the use of weak keepers to counteract charge leakage/sharing and thus to hold the dynamic signal value.
Known QDI circuits based on the Dynamic-Logic and Pass-Logic families and different variations thereof include differential cascode voltage swing logic (DCVSL), pre-charged half buffer, and mixed Dynamic-Logic/Pass-Logic/pseudo-Static-Logic. These QDI circuits can be found in literature, and are largely summarized in the abovementioned book authored by Sparso et al, and in a book authored by P. A. Beerel, R. O. Ozdag, and M. Ferretti and entitled ‘A Designer's Guide to Asynchronous VLSI’, Cambridge University Press, 2010 (herein Beerel et al). For sub-threshold operation, designs based on the Dynamic-Logic family are generally inapplicable or impractical due to their unreliability (poor robustness) and the associated critical sizing of transistors (especially for weak keepers) due to charge leakage/sharing. Similarly, QDI designs based on Pass-Logic family are impractical and not robust for sub-threshold operation due to either a weak logic ‘1’ transfer (for n-MOS pass-logic) or a weak logic ‘0’ transfer (for p-MOS pass-logic), resulting in poor noise margin. In other words, they suffer from weak current strength (especially when transistor stack is high). Furthermore, they often require weak keepers (which in turn require critical transistor sizing) for signal restoring/holding. On the other hand, designs based on the Static-Logic family are more reliable, in part because the associated sizing of transistors is not as critical and their level of noise margin is higher as compared to other logic families.
Reported QDI asynchronous-logic realization approaches based on Static-Logic family include NULL-convention-logic (NCL), Delay-Insensitive-Minterm-Synthesis (DIMS) and Direct Static-Logic Implementation (DSLI). However, these realizations based on these reported QDI realization approaches have relatively high overheads in terms of large IC area, long delays and high power/energy, in part because of their relatively complex realizations. These shortcomings are considerable in large digital systems because of the associated cost (large IC area), slow computation (long delay) and short battery lifespan (high power; or the need to accommodate higher heat).
In summary, the appropriate design methodology to operate digital circuits for full Dynamic Voltage Scaling (including for sub-threshold operation) is to adopt asynchronous-logic design philosophy, specifically the QDI approach with Static-Logic realization approach. At the juncture of technology, there is no operationally robust and yet ultra low power sub-threshold digital circuit, including those digital circuits based on the reported QDI realization approaches. Hence, it is highly desirable to have a design technique that is virtually insensitive to the PVT variations, and the associated attribute is operation robustness and yet ultra low power dissipation for sub-threshold digital circuits. This will be apparent later in this specification.